Research

Research & Publications

Technical papers, benchmarks, and production case studies on AI-assisted digital chip design. Every result here is reproducible and independently verified.

4 publications

Independently verified · reproducible results

White PaperApr 22, 2026REF · 01

From 40% to 100%: SAiGE Autonomously Closes the Loop on RTL Design

SAiGE writes the Verilog, runs the testbench, reads failures, fixes bugs, and iterates until the design passes — no human in the loop. Benchmarked on RTLLM 2.0 across major LLMs.

Result100%RTLLM 2.0, fully autonomous

Benchmark·Autonomous RTL

View PDF→

White PaperJun 6, 2026REF · 02

SAiGE on NVIDIA CVDP: A General-Purpose Agent Across Multi-Task Hardware Design

Strong performance as a general-purpose RTL agent across generation, modification, reuse, and bug fixing — positioning SAiGE as a practical system for real semiconductor workflows.

Result83%NVIDIA CVDP, no task-specific training

Benchmark·General-Purpose Agent

View PDF→

White PaperJun 21, 2026REF · 03

Closed-Loop Agentic Bug-Fixing on a Production RISC-V Vector Processor

Real RTL debugging on PULP Ara: 15 correctness bugs fixed across 7 modules, each validated against Spike, passing 18/18 regressions across 2–16 lanes.

Result15 bugsfixed across 7 RTL modules on PULP Ara

Bug-Fixing·RISC-V

View PDF→

White PaperJun 29, 2026REF · 04

A Confidence-Tiered Campaign on a Production EDA Toolchain: OpenROAD

SAiGE goes beyond RTL generation to debug a real production EDA toolchain — triaging 24 OpenROAD issues and producing 17 independently verified fixes.

Result17 / 24OpenROAD issues independently fixed

EDA Toolchain·Bug-Fixing

View PDF→

Get Started

Ready to transform your workflow?

See how SAiGE can accelerate your team's digital chip-design process.

Try SAiGE→

Have questions? Reach out directly at contact@fermions.co